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Silicon Labs /Series0 /EZR32HG /EZR32HG320F32R63 /DMA /CH2_CTRL

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Interpret as CH2_CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SIGSEL0 (NONE)SOURCESEL

SOURCESEL=NONE

Description

Channel Control Register

Fields

SIGSEL

Signal Select
SOURCESEL

Source Select

0 (NONE): No source selected

8 (ADC0): Analog to Digital Converter 0

12 (USART0): Universal Synchronous/Asynchronous Receiver/Transmitter 0

13 (USARTRF1): Universal Synchronous/Asynchronous Receiver/Transmitter 1

16 (LEUART0): Low Energy UART 0

20 (I2C0): I2C 0

24 (TIMER0): Timer 0

25 (TIMER1): Timer 1

26 (TIMER2): Timer 2

48 (MSC): undefined

49 (AES): Advanced Encryption Standard Accelerator

Links

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Register License

  • SPDX-License-Identifier: Zlib
  • The licensor of this software is Silicon Laboratories Inc.
  • This software is provided ‘as-is’, without any express or implied
  • warranty. In no event will the authors be held liable for any damages
  • arising from the use of this software.
  • Permission is granted to anyone to use this software for any purpose,
  • including commercial applications, and to alter it and redistribute it
  • freely, subject to the following restrictions:
    1. The origin of this software must not be misrepresented; you must not
  • claim that you wrote the original software. If you use this software
  • in a product, an acknowledgment in the product documentation would be
  • appreciated but is not required.
    1. Altered source versions must be plainly marked as such, and must not be
  • misrepresented as being the original software.
    1. This notice may not be removed or altered from any source distribution.
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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data